Embedded Wafer Level Ball Grid Array

From Infogalactic: the planetary knowledge core
Jump to: navigation, search

Lua error in package.lua at line 80: module 'strict' not found.

Embedded Wafer Level Ball Grid Array (eWLB) is a packaging technology for integrated circuits. The package interconnects are applied on an artificial wafer made of silicon chips and a casting compound.

File:EWLB Sketch e.png
Principle eWLB

eWLB is a further development of the classical Wafer Level Ball Grid Array Technology (WLB or WLP: wafer level package). The main driving force behind the eWLB technology was to allow fanout and more space for interconnect routing.

All process steps for the generation of the package are performed on the wafer. This allows, in comparison to classical packaging technologies (e. g. ball grid array), the generation of very small and flat packages with excellent electrical and thermal performance at lowest cost. It is common for all WLB technologies, which are built on a silicon wafer, that the interconnects (typically solder balls) fit on the chip (so called fan-in design). Therefore only chips with a restricted number of interconnects can be packaged.

File:EWLB Crossection e.png
Cross Section eWLB

The eWLB technology allows the realization of chips with a high number of interconnects. The package is not realized on a silicon wafer as for classical Wafer Level Package, but on an artificial wafer. Therefore a front-end-processed wafer is diced and the singulated chips are placed on a carrier. The distance between the chips can be chosen freely, but it is typically larger than on the silicon wafer. The gaps and the edges around the chips are now filled with a casting compound to form a wafer. After curing an artificial wafer containing a mold frame around the dies for carrying additional interconnect elements is realized. After the built of the artificial wafer (the so-called Reconstitution) the electrical connections from the chip pads to the interconnects are realized in thin-film technology, like for any other classical Wafer Level Package.

With this technology any number of additional interconnects can be realized on the package in an arbitrary distance (fan-out design). Therefore this Wafer Level Packaging Technology can also be used for space sensitive applications, where the chip area wouldn’t be sufficient to place the needed number of interconnects in a realizable distance. The eWLB Technology was developed by Infineon, STMicroelectronics and STATS ChipPAC Ltd.[1] First components were brought into market mid of 2009 (mobile phone).

Process Steps

  1. Lamination of foil onto carrier (Lamination tool)
  2. Chip placement onto wafer (Pick and place tool)
  3. Molding (Mold press)
  4. De-Bonding of carrier (de-bonding tool)
  5. Flip reconstructed wafer
  6. Ball drop reflow and wafer test

Advantages

  • Low cost (package and test)
  • Minimal lateral package size and height
  • Excellent electrical and thermal properties
  • Number of realizable interconnects on the package is not restricted
  • High integration potential for multi-die- and stacked packages
  • Upcoming package standard

Disadvantages

  • Inspection and repair difficult since visual inspection is restricted
  • Mechanical stress between package and board is transmitted stronger than for other package technologies

See also

References

  1. ↑ Infineon, ST and STATS Develops eWLB | TopNews United States
Retrieved from "https://infogalactic.com/w/index.php?title=Embedded_Wafer_Level_Ball_Grid_Array&oldid=4873056"