File:Mips32 addi.svg
Summary
This figure demonstrates how one type of MIPS32 instruction word is decoded. The first six bits specify the operation (add immediate). The second and third groups of five bits each specify the number of one of MIPS32's 32 general-purpose registers (GPR). The first group specifies the destination GPR, and the second specifies the source GPR. The last sixteen bits specify the immediate value, that is, the 16-bit signed (two's compliment) integer that is added to the second register and then stored in the first register. The equivalent mnemonic in MIPS32 assembly is also shown. This instruction word would cause a MIPS32 CPU to add 350 to the value stored in $r2 and store the result in $r1. If an arithmetic overflow occurs, $r1 is not modified and an overflow flag is set.
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 17:50, 3 January 2017 | | 500 × 180 (15 KB) | 127.0.0.1 (talk) | <p>This figure demonstrates how one type of MIPS32 instruction word is decoded. The first six bits specify the operation (add immediate). The second and third groups of five bits each specify the number of one of MIPS32's 32 general-purpose registers (GPR). The first group specifies the destination GPR, and the second specifies the source GPR. The last sixteen bits specify the immediate value, that is, the 16-bit signed (two's compliment) integer that is added to the second register and then stored in the first register. The equivalent mnemonic in MIPS32 assembly is also shown. This instruction word would cause a MIPS32 CPU to add 350 to the value stored in $r2 and store the result in $r1. If an arithmetic overflow occurs, $r1 is not modified and an overflow flag is set. </p> |
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