Memory timings

Memory timings or RAM timings measure the performance of DRAM memory using four parameters: CL, T_RCD, T_RP, and T_RAS in units of clock cycles; they are commonly written as four numbers separated with dashes, e.g. 7-8-8-24. The fourth (tRAS) is often omitted, and a fifth, the Command rate, sometimes added (normally 2T or 1T - also 2N, 1N). These parameters specify the latencies (time delays) that affect speed of random access memory. Lower numbers usually imply faster performance. What determines absolute system performance is actual latency time, usually measured in nanoseconds.

When translating memory timings into actual latency, it is important to note that they are in units of clock cycles, which for double data rate memory is half the speed of the commonly-quoted transfer rate.

For example, DDR3-2000 memory has a 1000 MHz clock frequency. With this 1 ns clock, CL=7 gives an absolute latency of 7 ns. Faster DDR3-2666 (with a 1333 MHz clock, or 0.75 ns per cycle), even with a longer CL=9, gives a shorter absolute latency of 6.75 ns.

Modern DIMMs include a Serial Presence Detect (SPD) ROM chip that contains recommended memory timings for automatic configuration. The BIOS on a PC may allow the user to make adjustments in an effort to increase performance (with possible risk of decreased stability) or, in some cases, to increase stability (by using suggested timings).

Note: Memory bandwidth measures the throughput of memory, and is closely related to memory timings. It is possible for advances in bandwidth technology to have an undesirable impact on latency. For example, DDR memory has been superseded by DDR2, and yet DDR2 has significantly higher latency at the same clock frequencies. However, DDR2 can be clocked faster, decreasing its cycle time. Now DDR2 has been superseded by DDR3, and the trend of a higher latency coupled with a higher clock speed has continued.

Increasing memory bandwidth, even while increasing memory latency, can improve the performance of a computer system with multiple processors, and also systems with processors that have multiple execution threads. Higher bandwidth will also boost performance of integrated graphics that have no dedicated video memory.

Name	Symbol	Definition
CAS latency	CL	The time between sending a column address to the memory and the beginning of the data in response. This is the time it takes to read the first bit of memory from a DRAM with the correct row already open.
Row Address to Column Address Delay	TRCD	The number of clock cycles required between the opening of a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is TRCD + CL.
Row Precharge Time	TRP	The number of clock cycles required between the issuing of the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is TRP + TRCD + CL.
Row Active Time	TRAS	The number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlapping with TRCD. In SDRAM modules, it is simply TRCD + CL. Otherwise, approximately equal to TRCD + (2 * CL).
Notes: RAS : Row Address Strobe CAS : Column Address Strobe TWR : Write Recovery Time, the time that must elapse between the last write command to a row and precharging it. Generally, TRAS = TRCD + TWR. TRC : Row Cycle Time. TRC = TRAS + TRP.

Handling in BIOS

In Intel systems, memory timings and management are handled by the Memory Reference Code (MRC), a part of the BIOS.