5 nanometer

In semiconductor manufacturing, the International Technology Roadmap for Semiconductors defines the 5 nanometer (5 nm) node as the technology node following the 7 nm node.

Transistors at the 7 nm scale were first produced by researchers in the first decade of the 21st century – the process scale may represent the end of Moore's Law scaling for electronic devices.

As of 2016, no 5 nm scale devices have been commercially produced.

History

Background

The 5 nm node was once assumed by some experts to be the end of Moore's law. Transistors smaller than 7 nm will experience quantum tunnelling through their logic gates. Due to the costs involved in development, 5 nm is predicted to take longer to reach market than the 2 years estimated by Moore's law.

Technology demos

In 2006, a team of Korean researchers from the Korea Advanced Institute of Science and Technology (KAIST) and the National Nano Fab Center codeveloped a 3 nm transistor, the world's smallest nanoelectronic device based on conventional technology, called a fin field-effect transistor (FinFET). It was the smallest transistor ever produced.

In 2008, transistors one atom thick and ten atoms wide were made by UK researchers. They were carved from graphene, a potential alternative to silicon as the basis of future computing. Graphene is a material made from flat sheets of carbon in a honeycomb arrangement, and is a leading contender. A team at the University of Manchester, UK, used it to make some of the smallest transistors at this time: devices only 1 nm across that contain just a few carbon rings.

In 2010, an Australian team announced that they fabricated a single functional transistor out of 7 atoms that measured 4 nm in length.

In 2012, a single-atom transistor was fabricated using a phosphorus atom bound to a silicon surface (between two significantly larger electrodes). This transistor could be said to be a 180 picometer transistor, the Van der Waals radius of a phosphorus atom; though its covalent radius bound to silicon is likely smaller. Making transistors smaller than this will require either using elements with smaller atomic radii, or using subatomic particles—like electrons or protons—as functional transistors.

In 2015 IMEC and Cadence had fabricated 5 nm test chips. The fabricated test chips are not fully functional devices but rather are to evaluate patterning of interconnect layers.

In 2015 Intel described a lateral nanowire (or gate-all-around) FET concept for the 5-nm node.

Commercialization

Although Intel has not yet divulged any certain plans to manufacturers or retailers, their 2009 roadmap projected an end-user release by approximately 2020.

References

Preceded by 7 nm

CMOS manufacturing processes

Succeeded by Nanotechnology