Cycle stealing

This article is about hardware memory operations. For the use of idle CPU time for distributed computation, see CPU scavenging.

Cycle stealing is a method of accessing RAM without interfering with the CPU. It is similar to DMA for allowing I/O controllers to read or write RAM without CPU intervention. Clever exploitation of specific CPU or bus timings could permit the CPU to run at full speed without any delay if external devices may sneak in one RAM access to memory not actively participating in the CPU's current activity and complete the operations before any possible CPU conflict. Such systems are nearly dual-port RAM without the expense of high speed RAM. Most systems halt the CPU during the steal, essentially making it DMA by another name.

For example, a system with separate instruction and data memory banks could allow external devices ONE memory access to the data RAM while the CPU was in op-code-fetch, if both accesses were initiated simultaneously. A MMU is not essential, for the Zilog Z80's M1 line could be used to distinguish instruction from data access, so while the CPU is reading an instruction from instruction-RAM or ROM, the data RAM is available to other devices without disturbing the CPU at all.

Modern architecture

Cycle stealing is difficult to achieve in modern systems due to many factors such as pipelining, pre-fetch and concurrent elements constantly accessing memory, leaving few predictable idle times to sneak in memory access. DMA is the only formal and predictable method for external devices to access RAM.

This term is less common in modern computer architecture (say above 66-100 MHz), where the various external buses and controllers generally run at different rates, and CPU internal operations are no longer closely coupled to I/O bus operations.

Examples in actual computer systems

Unexpected cycle stealing by the rendezvous radar during descent nearly caused the Apollo 11 landing to be aborted, but the design of the Apollo Guidance Computer allowed the landing to continue by dropping low-priority tasks.

The IBM system 1130's "cycle steal" is really DMA because the CPU clock is stopped during memory access. Several I/O controllers access RAM this way. They self-arbitrate via a fixed priority scheme. Most controllers deliberately pace RAM access to minimize impact on the system's ability to run instruction, but others are greedy (such as the graphic video adapter) and may slow down the system.

The cycle-stealing concept of the 1130

permits the CPU program to start an operation on an I/O device and then continue the mainline program while the I/O device is performing its operation. Each I/O device that operates in this manner takes (steals) a cycle from the CPU when it is needed.

The CPU is "tied up" only one cycle while a data character is being transferred. The frequency at which devices steal cycles depends on the type of device.

Since the CPU is much faster than any I/O device on the system, the CPU may be performing another function, such as arithmetic, at the same time an I/O operation is being performed. In fact, several I/O operations may be overlapped with each other and with other CPU functions.

Cycle stealing has been the cause of major performance degradation on machine such as the Sinclair QL, where, for economy reasons, the video RAM was not dual access. Consequently, the M68008 was denied access to the memory bus when the ZX8301 was accessing memory, and the machine performed poorly when compared with machines using similar processors at similar speeds.