File:5 Stage Pipeline.svg
From Infogalactic: the planetary knowledge core
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Original file (SVG file, nominally 300 × 190 pixels, file size: 33 KB)
Summary
A diagram showing the stage of execution reached by five consecutive instructions in a 5-stage microprocessor. At clock cycle 4, the 1st instruction is in the "memory access" phase, the second is in the "execute" phase, the third in the "instruction decode" phase, the fourth in the "instruction fetch" phase and the fifth hasn't been fetched yet.
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File history
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| Date/Time | Thumbnail | Dimensions | User | Comment | |
|---|---|---|---|---|---|
| current | 10:53, 3 January 2017 | | 300 × 190 (33 KB) | 127.0.0.1 (talk) | A diagram showing the stage of execution reached by five consecutive instructions in a 5-stage microprocessor. At clock cycle 4, the 1st instruction is in the "memory access" phase, the second is in the "execute" phase, the third in the "instruction decode" phase, the fourth in the "instruction fetch" phase and the fifth hasn't been fetched yet. |
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